307 lines
9.8 KiB
C
307 lines
9.8 KiB
C
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// Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) All rights reserved.
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// SPDX-License-Identifier: Apache-2.0
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#include <openssl/base.h>
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#include "internal.h"
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#if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
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#ifndef __STDC_FORMAT_MACROS
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#define __STDC_FORMAT_MACROS
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#endif
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#if defined(_MSC_VER)
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OPENSSL_MSVC_PRAGMA(warning(push, 3))
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#include <immintrin.h>
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#include <intrin.h>
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OPENSSL_MSVC_PRAGMA(warning(pop))
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#endif
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// OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
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// is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
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// |*out_edx|.
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static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
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uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
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#if defined(_MSC_VER)
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int tmp[4];
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__cpuid(tmp, (int)leaf);
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*out_eax = (uint32_t)tmp[0];
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*out_ebx = (uint32_t)tmp[1];
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*out_ecx = (uint32_t)tmp[2];
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*out_edx = (uint32_t)tmp[3];
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#elif defined(__pic__) && defined(OPENSSL_32_BIT)
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// Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
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// See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
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__asm__ volatile (
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"xor %%ecx, %%ecx\n"
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"mov %%ebx, %%edi\n"
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"cpuid\n"
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"xchg %%edi, %%ebx\n"
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: "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf)
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);
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#else
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__asm__ volatile (
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"xor %%ecx, %%ecx\n"
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"cpuid\n"
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: "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf)
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);
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#endif
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}
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// OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
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// Currently only XCR0 is defined by Intel so |xcr| should always be zero.
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static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
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#if defined(_MSC_VER)
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return (uint64_t)_xgetbv(xcr);
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#else
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uint32_t eax, edx;
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#if defined(MY_ASSEMBLER_IS_TOO_OLD_FOR_AVX)
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// Some old assemblers don't support the xgetbv instruction so we emit
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// the opcode of xgetbv directly.
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__asm__ volatile (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
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#else
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__asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
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#endif
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return (((uint64_t)edx) << 32) | eax;
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#endif
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}
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static bool os_supports_avx512(uint64_t xcr0) {
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#if defined(OPENSSL_APPLE)
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// The Darwin kernel had a bug where it could corrupt the opmask registers.
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// See
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// https://community.intel.com/t5/Software-Tuning-Performance/MacOS-Darwin-kernel-bug-clobbers-AVX-512-opmask-register-state/m-p/1327259
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// Darwin also does not initially set the XCR0 bits for AVX512, but they are
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// set if the thread tries to use AVX512 anyway. Thus, to safely and
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// consistently use AVX512 on macOS we'd need to check the kernel version as
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// well as detect AVX512 support using a macOS-specific method. We don't
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// bother with this, especially given Apple's transition to arm64.
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return false;
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#else
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return (xcr0 & 0xe6) == 0xe6;
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#endif
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}
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// handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
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// and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this.
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static void handle_cpu_env(uint32_t *out, const char *in) {
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const int invert = in[0] == '~';
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const int or = in[0] == '|';
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const int skip_first_byte = invert || or;
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const int hex = in[skip_first_byte] == '0' && in[skip_first_byte+1] == 'x';
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uint32_t intelcap0 = out[0];
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uint32_t intelcap1 = out[1];
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int sscanf_result;
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uint64_t v;
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if (hex) {
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sscanf_result = sscanf(in + skip_first_byte + 2, "%" PRIx64, &v);
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} else {
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sscanf_result = sscanf(in + skip_first_byte, "%" PRIu64, &v);
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}
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if (!sscanf_result) {
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return;
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}
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uint32_t reqcap0 = (uint32_t)(v & UINT32_MAX);
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uint32_t reqcap1 = (uint32_t)(v >> 32);
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// Detect if the user is trying to use the environment variable to set
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// a capability that is _not_ available on the CPU.
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// The case of invert cannot enable an unexisting capability;
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// it can only disable an existing one.
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if (!invert && (intelcap0 || intelcap1)) {
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// Allow Intel indicator bit to be set for testing
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if((~(1u << 30 | intelcap0) & reqcap0) || (~intelcap1 & reqcap1)) {
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fprintf(stderr,
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"Fatal Error: HW capability found: 0x%02X 0x%02X, but HW capability requested: 0x%02X 0x%02X.\n",
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intelcap0, intelcap1, reqcap0, reqcap1);
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abort();
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}
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}
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if (invert) {
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out[0] &= ~reqcap0;
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out[1] &= ~reqcap1;
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} else if (or) {
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out[0] |= reqcap0;
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out[1] |= reqcap1;
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} else {
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out[0] = reqcap0;
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out[1] = reqcap1;
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}
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}
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extern uint8_t OPENSSL_cpucap_initialized;
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static int amd_rdrand_maybe_apply_restrictions(const uint32_t family,
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const uint32_t model) {
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// Disable RDRAND on AMD families before 0x17 (Zen) due to reported failures
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// after suspend. https://bugzilla.redhat.com/show_bug.cgi?id=1150286
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// Also disable for family 0x17, models 0x70–0x7f, due to possible RDRAND
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// failures there too.
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if (family < 0x17 || (family == 0x17 && 0x70 <= model && model <= 0x7f)) {
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return 1;
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}
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// Zen2 EPYC have prohibitively slow RDRAND implementations. Specifically,
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// measured on the model EPYC 7R32. Please see q/VxC3AiwXpAjJ.
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// We assume that slow implementations is universal to all AMD models based
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// on the Zen2 uarch. Additionally, extend this assumptions to Zen1 based
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// AMD models as well because Zen1 and Zen2 shares family number.
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if (family == 0x17) {
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return 1;
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}
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// No restrictions.
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return 0;
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}
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void OPENSSL_cpuid_setup(void) {
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// Determine the vendor and maximum input value.
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uint32_t eax, ebx, ecx, edx;
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
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uint32_t num_ids = eax;
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int is_intel = ebx == 0x756e6547 /* Genu */ &&
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edx == 0x49656e69 /* ineI */ &&
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ecx == 0x6c65746e /* ntel */;
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int is_amd = ebx == 0x68747541 /* Auth */ &&
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edx == 0x69746e65 /* enti */ &&
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ecx == 0x444d4163 /* cAMD */;
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uint32_t extended_features[2] = {0};
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if (num_ids >= 7) {
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
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extended_features[0] = ebx;
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extended_features[1] = ecx;
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}
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
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if (is_amd) {
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// See https://www.amd.com/system/files/TechDocs/25481.pdf, page 10.
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const uint32_t base_family = (eax >> 8) & 15;
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const uint32_t base_model = (eax >> 4) & 15;
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uint32_t family = base_family;
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uint32_t model = base_model;
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if (base_family == 0xf) {
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const uint32_t ext_family = (eax >> 20) & 255;
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family += ext_family;
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const uint32_t ext_model = (eax >> 16) & 15;
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model |= ext_model << 4;
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}
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if (amd_rdrand_maybe_apply_restrictions(family, model) != 0) {
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ecx &= ~(1u << 30);
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}
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}
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// Force the hyper-threading bit so that the more conservative path is always
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// chosen.
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edx |= 1u << 28;
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// Reserved bit #20 was historically repurposed to control the in-memory
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// representation of RC4 state. Always set it to zero.
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edx &= ~(1u << 20);
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// Reserved bit #30 is repurposed to signal an Intel CPU.
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if (is_intel) {
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edx |= (1u << 30);
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// Clear the XSAVE bit on Knights Landing to mimic Silvermont. This enables
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// some Silvermont-specific codepaths which perform better. See OpenSSL
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// commit 64d92d74985ebb3d0be58a9718f9e080a14a8e7f and
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// |CRYPTO_cpu_perf_is_like_silvermont|.
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if ((eax & 0x0fff0ff0) == 0x00050670 /* Knights Landing */ ||
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(eax & 0x0fff0ff0) == 0x00080650 /* Knights Mill (per SDE) */) {
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ecx &= ~(1u << 26);
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}
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} else {
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edx &= ~(1u << 30);
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}
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// The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD
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// XOP code paths.
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ecx &= ~(1u << 11);
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uint64_t xcr0 = 0;
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if (ecx & (1u << 27)) {
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// XCR0 may only be queried if the OSXSAVE bit is set.
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xcr0 = OPENSSL_xgetbv(0);
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}
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// See Intel manual, volume 1, section 14.3.
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if ((xcr0 & 6) != 6) {
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// YMM registers cannot be used.
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ecx &= ~(1u << 28); // AVX
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ecx &= ~(1u << 12); // FMA
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ecx &= ~(1u << 11); // AMD XOP
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// Clear AVX2 and AVX512* bits.
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//
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// TODO(davidben): Should bits 17 and 26-28 also be cleared? Upstream
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// doesn't clear those. See the comments in
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// |CRYPTO_hardware_supports_XSAVE|.
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extended_features[0] &=
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~((1u << 5) | (1u << 16) | (1u << 21) | (1u << 30) | (1u << 31));
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}
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// See Intel manual, volume 1, section 15.2.
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if (!os_supports_avx512(xcr0)) {
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// Clear AVX512F. Note we don't touch other AVX512 extensions because they
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// can be used with YMM.
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extended_features[0] &= ~(1u << 16);
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}
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// Disable ADX instructions on Knights Landing. See OpenSSL commit
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// 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
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if ((ecx & (1u << 26)) == 0) {
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extended_features[0] &= ~(1u << 19);
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}
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OPENSSL_ia32cap_P[0] = edx;
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OPENSSL_ia32cap_P[1] = ecx;
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OPENSSL_ia32cap_P[2] = extended_features[0];
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OPENSSL_ia32cap_P[3] = extended_features[1];
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OPENSSL_cpucap_initialized = 1;
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const char *env1, *env2;
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env1 = getenv("OPENSSL_ia32cap");
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if (env1 == NULL) {
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return;
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}
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// OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
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// Each value is a 64-bit, unsigned value which may start with "0x" to
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// indicate a hex value. Prior to the 64-bit value, a '~' or '|' may be given.
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//
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// If the '~' prefix is present:
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// the value is inverted and ANDed with the probed CPUID result
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// If the '|' prefix is present:
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// the value is ORed with the probed CPUID result
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// Otherwise:
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// the value is taken as the result of the CPUID
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//
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// The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
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// and [3].
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handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
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env2 = strchr(env1, ':');
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if (env2 != NULL) {
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handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
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}
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}
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#endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)
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